CTPCI : Project story

October 28th, 2008

Routing is finished. Verifications are OK. Next step : prototype. Mainboard & PCIboard .

September 2008

Autorouter try : 97.4% of 1138 nets. Stills some settings to be done, some manual PCB work, some parts to be validated and tuning of the clocks traces : CTPCI.gif.

September 2007 to March 2008

The hierarchical schematics are finished. This design method allows the reuse of some blocks in some others designs... I will so continue to layout of the boards with need to create some parts in the library...  I present you the 'TOP' sheet of the CTPCI project : the blocks point to schematics sheet. Here is the PLX sheet.

August 2007

Happy getting a bit money to buy some parts to assemble a powerfull PC in my week appartement to run Dx Designer & Pads Layout + Router software flow from Mentor Graphics. I get a licence that costs 6000€...  

January to June 2007

The project is going slowly because of my job far from my house and so some heavy days and shorts week ends... Finally I finished the design of the CPLD and I will go back to schematics.

September 2006

After a long period very busy, I go back on CTPCI design...

I try to find a better CAD software to boost the PCB design.

May 2006

Thought about a new IDE port : negative (no place & may be available on PCI).

April 2006

Deepened study of the PLX 9054 to determine the logic conception with the CT bus.

Study the PCI-->Local (PCI master & DMA) data transfert rates according to the technical choices for the 'glue' logic : CPLD or FPGA.

March 2006

Project on the rails again.

PCI knowledges refresh.

Start the writing of the developers documentation (CTPCI Hardware Guide).

November 2005

Confirmation the project can be developed.

Project stopped.

August 2005

Announcement of the project and opinion testing among the CT users.